Today's integrated circuits are deeply complex in many ways. A dozen or so years ago, a state-of-the-art processor had approximately 40 million transistors, was built on a 180 nm process and relied upon discrete chips to handle its system interfaces. A processor introduced in 2012 had 2.6 billion transistors and was built on a 32 nm process. The very same chip included ten 64-bit cores, L3 cache, graphics processing, DDR3 interfaces, and more. The trend to massive integration is even stronger in the mobile space, where systems on chip (SoC) bring together complex computing, communications and entertainment functions on a single die. Furthermore, clock and reset distribution networks became ubiquitous as they traverse across SoCs feeding all sequential elements while meeting aggressive timing parameters, signal integrity and, in particular, power dissipation specifications. The drive to pack more functions into a small space leads to power delivery and heat flux issues affecting supply integrity and chip packaging. Power issues, however, are not confined to the mission mode. Toggling rates and the resultant power consumption are much higher than a circuit is rated for during structural scan-based testing as the testing goal is to activate as many nodes as possible in the shortest test time. This trend is only expected to continue. The resulting higher junction temperature and increased peak power lead to overheating or supply voltage noise—either of which can cause a device malfunction, and thus yield loss, chip reliability degradation, shorter product lifetime, or device permanent damage.
Over the years, numerous techniques for power reduction of scan testing have been proposed. Test scheduling and vector reordering, partitioning and modifications of scan chains, gating of scan cells, low power test generators, transition blocking and clock gating are all aimed at keeping the power dissipation below a given threshold. A thorough survey of these methods can be found in Power-Aware Testing and Test Strategies for Low Power Devices, P. Girard, N. Nicolici, X. Wen (ed.), Springer, New York 2010, which is incorporated herein by reference. Similar techniques have also been proposed for a variety of BIST applications.
The advent of power-aware ATPG (automatic test pattern generation) has added a new dimension to low power testing. Solutions in this group tailor test patterns to the requirements of test application with reduced switching activity. Instead of random fill, unspecified positions of deterministic test vectors assume values minimizing the number of transitions during scan shifting. For example, don't-care bits may assume a constant value or be replicated by using the most recent care bit for all unspecified positions until the next specified bit whose value is used for the following (adjacent) positions.
Test data compression or test compression also faces similar problems related to test power dissipation. In addition to reducing data volume, test time, and test pin counts, several test compression schemes have been able to successfully limit scan toggling. Some of them enhance conventional LFSR (linear feedback shift register) reseeding techniques to reduce the scan-in transition probability. Among them, one method uses two LFSRs to produce tests and corresponding masks. Outputs of the two LFSRs are subsequently merged to decrease the amount of switching. Another method divides test cubes into blocks and uses reseeding to encode blocks with transitions. A constant value fed directly to scan chains replaces other blocks.
The embedded deterministic test (EDT) is a test data compression technology developed by Mentor Graphics Corporation (Wilsonville, Oreg.). Details concerning the EDT technology are provided in J. Rajski, J. Tyszer, M. Kassab, and N. Mukherjee, “Embedded deterministic test,” IEEE Trans. CAD, vol. 23, pp. 776-792, May 2004, and U.S. Pat. Nos. 6,327,687; 6,353,842; 6,539,409; 6,543,020; 6,557,129; 6,684,358; 6,708,192; 6,829,740; 6,874,109; 7,093,175; 7,111,209; 7,260,591; 7,263,641; 7,478,296; 7,493,540; 7,500,163; 7,506,232; 7,509,546; 7,523,372; 7,653,851, all of which are hereby incorporated herein by reference. One low power method applicable to the EDT scheme uses available encoding capacity to limit transitions in scan chains. Unlike reseeding-based schemes, this technique freezes a decompressor in certain states. It allows loading scan chains with patterns having low transition counts. Details concerning the method are provided in U.S. Pat. Nos. 7,797,603, 7,647,540, 8,015,461, 8,301,945 and 8,046,653, which are hereby incorporated herein by reference.
In another method applicable to the EDT scheme, low toggling data may be provided to scan chains for a number of shift cycles through a hold register placed in the middle of decompressor. It retains, for a number of cycles, a desired state of the generator, while the generator itself keeps advancing to the next state. The method may employ a power-aware scan controller operating as a linear decompressor. The power-aware scan controller may gate-off scan chains in a per pattern manner based on encoded test data. Details concerning the method are provided in U.S. Pat. Nos. 7,925,465 and 8,290,738, which are hereby incorporated herein by reference.
In still another method, a simple broadcasting of a constant value to predetermined groups of scan chains is employed. Such an approach makes provision for reducing the switching activity to a desired level by using a small amount of control data while test coverage remains intact. Details concerning the method are provided in M. Filipek, et al., “Low Power Decompression and PRPG with Constant Value Broadcast”, Proc. ATS, pp. 84-89, 2011 (“Filipek”), which is hereby incorporated herein by reference.
While many low power testing methods have been developed, challenges still remain in achieving power consumption reduction without increasing pattern counts (and thus test time).